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29.3.10 LCD Interrupt
The LCD interrupt can be used to synchronize data update. The FC interrupt flag is set at every LCD
Frame Counter Event, which must be set-up separately. The interrupt is enabled by setting FC bit in
LCD_IEN.
29.3.11 Blink, Blank, and Animation Features
29.3.11.1 Blink
The LCD driver can be configured to blink, alternating all enabled segments between on and off. The blink
frequency is given by the CLK EVENT frequency, see Section 29.3.9 (p. 430) . See Section 29.3.8 (p.
430) for details regarding synchronization of the blink feature. The FC must be on for blink to work.
29.3.11.2 Blank
Setting BLANK in LCD_BACTRL will output the “OFF” waveform on all enabled segments, effectively
blanking the entire display. Writing the BLANK bit to zero disables the blanking and segment data will
be output as normal. See Section 29.3.8 (p. 430) for details regarding synchronization of blank.
29.3.11.3 Animation State Machine
The Animation State Machine makes it possible to enable different animations without updating the data
registers, allowing specialized patterns running on the LCD panel while the microcontroller remains in
Low Energy Mode and thus saving power consumption. The animation feature is available on segment 0
to 7 multiplexed with LCD_COM0. The animation is implemented as two programmable 8 bits registers
that are shifted left or right every other Animation state for a total of 16 states.
The shift operations applied to the shift registers are controlled by AREGASC and AREGBSC in
LCD_BACTRL as shown in the table below. Note also that the FC must be on for animation to work, as
it is the FC event that drives the animation state machine.
Table 29.12. LCD Animation Shift Register
AREGnSC, n = A
or B
00
01
10
11
Mode
NOSHIFT
SHIFTLEFT
SHIFTRIGHT
Reserved
Description
No Shift operation
Animation register is shifted left (LCD_AREGA is shifted every odd state,
LCD_AREGB is shifted every even state)
Animation register is shifted right (LCD_AREGA is shifted every odd state,
LCD_AREGB is shifted every even state)
Reserved
The two registers are either OR’ed or AND’ed to achieve the displayed animation pattern. This is
controlled by ALOGSEL in LCD_BACTRL as shown in Table 29.13 (p. 432) . In addition, the regular
segment data SEGD0[7:0] is OR’ed with the animation pattern to generate the resulting output.
Table 29.13. LCD Animation Pattern
ALOGSEL
0
1
Mode
AND
OR
Description
LCD_AREGA and LCD_AREGB are AND’ed together
LCD_AREGA and LCD_AREGB are OR’ed together
Each state is displayed one CLK EVENT period, see Section 29.3.9 (p. 430) . By reading ASTATE in
LCD_STATUS, software can identify which state that is currently active in the state sequence. Note that
2011-04-12 - d0001_Rev1.10
432
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